01 / SELECTED WORK
Things I’ve built.
Hardware, systems and ML.
PROJECTS / 01 TO 04PICK A PROJECT ↘
I took a cache from Verilog to physical layout.
I built a cache with two ways per set, write back, and LRU replacement. I verified it against a Python model and ran it through physical design with LibreLane.
01REQUEST02TAG + SET03HIT?04WAY 005WAY 106MEMORY
3 cyclesrepeated cache hit · 9 cycles for external memory
Timing closed at 50 MHz. I'm preparing it for tapeout.
VERILOG / COCOTB / LIBRELANERead project