01 / SILICON2026

Tiny Cache

I took a cache from Verilog to physical layout.

2 waysper set · write back · LRU replacement

50 MHztiming closure

833cells in physical design

Physical layout of Sritej’s Tiny Cache design, showing placed cells and routing — 01 / PHYSICAL DESIGNTiny Cache · physical layout · preparing for tapeoutOriginal ↗

How it works

I built Tiny Cache in Verilog with two ways per set, write back, and LRU replacement within each set. It sits between a requester and external memory. A repeated cache hit takes three cycles, compared with nine cycles for an external memory access.

Physical design

I ran the design through LibreLane. The layout contains 833 cells and 152 flip flops in 14,568 µm², using 54% of one tile. Timing closed at 50 MHz with 10.47 ns of worst setup slack. Across three corners, the flow reported no hold, maximum capacitance, or maximum slew violations.

Testing and tapeout

I used cocotb to check the RTL and the synthesized gate level design against a Python reference model. The tests replay 300 randomized reads and writes with randomized memory latency. I also profiled hit rates for specific workloads. I'm preparing the design for tapeout.

NEXT PROJECTMini Redis